`include "para_def.v"
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:02:58 07/19/2013
// Design Name:   stage3
// Module Name:   D:/Xilinx/stage3/stage3_4_tb.v
// Project Name:  stage3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: stage3
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module stage3_4_tb;

	reg msg_end_1_2;
   reg valid_1_2;
	integer counter;
	reg [7:0] data_test [0:100];
	wire [7:0] data_1_2;

	// Inputs
	reg clk;
	reg rst_n;
	wire valid_2_3;
	wire [49:0] sel_2_3;
	wire [3:0] field_counter_2_3;
	wire [7:0] data_2_3;
	wire msg_end_2_3;

	// Outputs
	wire msg_end_3_4;
	wire [7:0] ID_0;
	wire [7:0] ID_1;
	wire [7:0] ID_2;
	wire [7:0] ID_3;
	wire [79:0] ID_4;
	wire [71:0] ID_5;
	wire [39:0] ID_6;
	wire [7:0] ID_7;
	wire [15:0] ID_8;
	wire [15:0] ID_9;
	wire [7:0] ID_10;
	wire [7:0] ID_11;
	wire [7:0] ID_12;
	wire [7:0] ID_13;
	wire [7:0] ID_14;
	wire [7:0] ID_15;
	wire [7:0] ID_16;
	wire [7:0] ID_17;
	wire [7:0] ID_18;
	wire [7:0] ID_19;
	wire [7:0] ID_20;
	wire [7:0] ID_21;
	wire [7:0] ID_22;
	wire [7:0] ID_23;
	wire [7:0] ID_24;
	wire [7:0] ID_25;
	wire [7:0] ID_26;
	wire [7:0] ID_27;
	wire [7:0] ID_28;
	wire [7:0] ID_29;
	wire [7:0] ID_30;
	wire [7:0] ID_31;
	wire [7:0] ID_32;
	wire [7:0] ID_33;
	wire [7:0] ID_34;
	wire [7:0] ID_35;
	wire [7:0] ID_36;
	wire [7:0] ID_37;
	wire [7:0] ID_38;
	wire [7:0] ID_39;
	wire [7:0] ID_40;
	wire [7:0] ID_41;
	wire [7:0] ID_42;
	wire [7:0] ID_43;
	wire [7:0] ID_44;
	wire [7:0] ID_45;
	wire [7:0] ID_46;
	wire [7:0] ID_47;
	wire [7:0] ID_48;
	wire [7:0] ID_49;
	wire valid;
	wire [63:0] data_out;

	// Instantiate the Unit Under Test (UUT)
	stage3 s3 (
		.clk(clk), 
		.rst_n(rst_n), 
		.valid_2_3(valid_2_3), 
		.sel_2_3(sel_2_3), 
		.field_counter_2_3(field_counter_2_3), 
		.data_2_3(data_2_3), 
		.msg_end_2_3(msg_end_2_3), 
		.msg_end_3_4(msg_end_3_4), 
		.ID_0(ID_0), 
		.ID_1(ID_1), 
		.ID_2(ID_2), 
		.ID_3(ID_3), 
		.ID_4(ID_4), 
		.ID_5(ID_5), 
		.ID_6(ID_6), 
		.ID_7(ID_7), 
		.ID_8(ID_8), 
		.ID_9(ID_9), 
		.ID_10(ID_10), 
		.ID_11(ID_11), 
		.ID_12(ID_12), 
		.ID_13(ID_13), 
		.ID_14(ID_14), 
		.ID_15(ID_15), 
		.ID_16(ID_16), 
		.ID_17(ID_17), 
		.ID_18(ID_18), 
		.ID_19(ID_19), 
		.ID_20(ID_20), 
		.ID_21(ID_21), 
		.ID_22(ID_22), 
		.ID_23(ID_23), 
		.ID_24(ID_24), 
		.ID_25(ID_25), 
		.ID_26(ID_26), 
		.ID_27(ID_27), 
		.ID_28(ID_28), 
		.ID_29(ID_29), 
		.ID_30(ID_30), 
		.ID_31(ID_31), 
		.ID_32(ID_32), 
		.ID_33(ID_33), 
		.ID_34(ID_34), 
		.ID_35(ID_35), 
		.ID_36(ID_36), 
		.ID_37(ID_37), 
		.ID_38(ID_38), 
		.ID_39(ID_39), 
		.ID_40(ID_40), 
		.ID_41(ID_41), 
		.ID_42(ID_42), 
		.ID_43(ID_43), 
		.ID_44(ID_44), 
		.ID_45(ID_45), 
		.ID_46(ID_46), 
		.ID_47(ID_47), 
		.ID_48(ID_48), 
		.ID_49(ID_49)
	);
	
	stage4 s4 (
		.clk(clk), 
		.rst_n(rst_n), 
		.msg_end_3_4(msg_end_3_4), 
		.ID_0(ID_0), 
		.ID_1(ID_1), 
		.ID_2(ID_2), 
		.ID_3(ID_3), 
		.ID_4(ID_4), 
		.ID_5(ID_5), 
		.ID_6(ID_6), 
		.ID_7(ID_7), 
		.ID_8(ID_8), 
		.ID_9(ID_9), 
		.ID_10(ID_10), 
		.ID_11(ID_11), 
		.ID_12(ID_12), 
		.ID_13(ID_13), 
		.ID_14(ID_14), 
		.ID_15(ID_15), 
		.ID_16(ID_16), 
		.ID_17(ID_17), 
		.ID_18(ID_18), 
		.ID_19(ID_19), 
		.ID_20(ID_20), 
		.ID_21(ID_21), 
		.ID_22(ID_22), 
		.ID_23(ID_23), 
		.ID_24(ID_24), 
		.ID_25(ID_25), 
		.ID_26(ID_26), 
		.ID_27(ID_27), 
		.ID_28(ID_28), 
		.ID_29(ID_29), 
		.ID_30(ID_30), 
		.ID_31(ID_31), 
		.ID_32(ID_32), 
		.ID_33(ID_33), 
		.ID_34(ID_34), 
		.ID_35(ID_35), 
		.ID_36(ID_36), 
		.ID_37(ID_37), 
		.ID_38(ID_38), 
		.ID_39(ID_39), 
		.ID_40(ID_40), 
		.ID_41(ID_41), 
		.ID_42(ID_42), 
		.ID_43(ID_43), 
		.ID_44(ID_44), 
		.ID_45(ID_45), 
		.ID_46(ID_46), 
		.ID_47(ID_47), 
		.ID_48(ID_48), 
		.ID_49(ID_49), 
		.valid(valid), 
		.data_out(data_out)
	);
	
	field_spliter fp_test(
        .rst_n(rst_n),
        .clk(clk),
        .valid_1_2(valid_1_2),
        .data_1_2(data_1_2),
        .msg_end_1_2(msg_end_1_2),
        .valid_2_3(valid_2_3),
        .data_2_3(data_2_3),
        .sel_2_3(sel_2_3),
        .field_counter_2_3(field_counter_2_3),
        .msg_end_2_3(msg_end_2_3)
    );


initial
    begin
        $readmemh("test_data.txt",data_test);
        counter=0;
        rst_n=0;
        clk=0;
        msg_end_1_2=0;
        valid_1_2=0;
        #12
        rst_n=1;
		  
		  #1000
        valid_1_2=1;
        #90
        msg_end_1_2=1;
        #10
        msg_end_1_2=0;
		  valid_1_2=0;
    end
    
    always #5 clk=~clk;
    
    always @(posedge clk)
    begin
        if(rst_n&valid_1_2)
            counter <= counter+1;
    end
    assign data_1_2=data_test[counter];
      
endmodule

